vishay siliconix SIA921EDj document number: 64734 s12-2731-rev. c, 12-nov-12 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com dual p-channel 20 v (d-s) mosfet features ? trenchfet ? power mosfet ? thermally enhanced powerpak ? sc-70 package - small footprint area - low on-resistance ? typical esd protection: 1700 v ? high speed switching ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? load switch, pa switch and battery switch for portable devices ? dc/dc converters notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. see solder profile ( www.vishay.com/doc?73257 ). the powerpak sc-70 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulat ion process in manufacturing. a solder fi llet at the exposed copper tip cannot be guara nteed and is not required to ensure adequate bottom side solder interconnection. e. rework conditions: manual solder ing with a soldering iron is not recommended for leadless components. f. maximum under steady state conditions is 110 c/w. product summary v ds (v) r ds(on) ( ? )i d (a) q g (typ.) - 20 0.059 at v gs = - 4.5 v - 4.5 a 4.9 nc 0.098 at v gs = - 2.5 v - 4.5 a s 1 d 1 g 2 s 2 g 1 d 2 1 6 5 4 2 3 2.05 mm 2.05 mm powerpak sc-70-6 dual d 1 d 2 orderin g information: SIA921EDj-t1-ge3 (lead (p b )-free and halogen-free) SIA921EDj-t4-ge3 (lead (p b )-free and halogen-free) markin g code x x x d f x lot tracea b ility and date code part # code p-channel mosfet s 2 d 2 g 2 p-channel mosfet s 1 d 1 g 1 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 20 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) t c = 25 c i d - 4.5 a a t c = 70 c - 4.5 a t a = 25 c - 4.5 a, b, c t a = 70 c - 3.7 b, c pulsed drain current i dm - 15 continuous source-drain diode current t c = 25 c i s - 4.5 a t a = 25 c - 1.6 b, c maximum power dissipation t c = 25 c p d 7.8 w t c = 70 c 5 t a = 25 c 1.9 b, c t a = 70 c 1.2 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) d, e 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, f t ? 5 s r thja 52 65 c/w maximum junction-to-case (drain) steady state r thjc 12.5 16
www.vishay.com 2 document number: 64734 s12-2731-rev. c, 12-nov-12 vishay siliconix SIA921EDj this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 20 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 14 mv/c v gs(th) temperature coefficient ? v gs(th) /t j 2.5 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.5 - 1.4 v gate-source leakage i gss v ds = 0 v, v gs = 4.5 v 1 a v ds = 0 v, v gs = 12 v 10 zero gate voltage drain current i dss v ds = - 20 v, v gs = 0 v - 1 v ds = - 20 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds ?? - 5 v, v gs = - 4.5 v - 15 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 3.6 a 0.048 0.059 ? v gs = - 2.5 v, i d = - 1.5 a 0.080 0.098 forward transconductance a g fs v ds = - 10 v, i d = - 3.6 a 11 s dynamic b total gate charge q g v ds = - 10 v, v gs = - 10 v, i d = - 4.7 a 15 23 nc v ds = - 10 v, v gs = - 4.5 v, i d = - 4.7 a 7.1 11 gate-source charge q gs 1.3 gate-drain charge q gd 2.1 gate resistance r g f = 1 mhz 6.3 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 2.7 ? i d ? - 3.7 a, v gen = - 4.5 v, r g = 1 ? 20 30 ns rise time t r 20 30 turn-off delay time t d(off) 25 40 fall time t f 10 15 tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 2.7 ? i d ? - 3.7 a, v gen = - 10 v, r g = 1 ? 510 rise time t r 12 20 turn-off delay time t d(off) 25 40 fall time t f 10 15 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 4.5 a pulse diode forward current i sm - 15 body diode voltage v sd i s = - 3.7 a, v gs = 0 v - 0.9 - 1.2 v body diode reverse recovery time t rr i f = - 3.7 a, di/dt = 100 a/s, t j = 25 c 15 30 ns body diode reverse recovery charge q rr 612nc reverse recovery fall time t a 8.5 ns reverse recovery rise time t b 6.5
vishay siliconix SIA921EDj document number: 64734 s12-2731-rev. c, 12-nov-12 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate current vs. gate-to-source voltage output characteristics on-resistance vs. drain current and gate voltage v gs - gate-to-so u rce v oltage ( v ) i g - gate c u rrent (ma) 0.0 0.1 0.2 0.3 0.4 0.5 036912151 8 i gss at 25 c (ma) 0 3 6 9 12 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs =10 v thr u 3 v v gs =1.5 v v gs =2.5 v v gs =2 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0.00 0.05 0.10 0.15 0.20 0 3 6 9 12 15 v gs = 2.5 v v gs =4.5 v - on-resistance ( ) r ds(on) i d - drain c u rrent (a) gate current vs. gate-to-source voltage transfer characteristics capacitance v gs - gate-to-so u rce v oltage ( v ) i g - gate c u rrent (a) 10 -10 10 -9 10 - 8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 036912151 8 i gss at 150 c i gss at 25 c 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 t c = 25 c t c = 125 c t c =- 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d c rss 0 200 400 600 8 00 1000 04 8 12 16 20 c iss c oss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf)
www.vishay.com 4 document number: 64734 s12-2731-rev. c, 12-nov-12 vishay siliconix SIA921EDj this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate charge source-drain diode forward voltage threshold voltage 0 2 4 6 8 10 0 3 6 9 12 15 i d =4.6a v ds =16 v v ds =10 v - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 10 1 100 t j = 25 c t j = 150 c v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 0.4 0.5 0.6 0.7 0. 8 0.9 1.0 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.7 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 - 50 - 25 0 25 50 75 100 125 150 i d =3.6a v gs =4.5 v v gs = 2.5 v t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) 0.00 0.05 0.10 0.15 0.20 012345 i d = 1 a; t j = 25 c i d = 1 a; t j = 125 c i d =3.6a;t j = 25 c i d =3.6a;t j = 125 c - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) 1000 100 1 0.001 0.01 0.1 10 po w er ( w ) p u lse (s) 20 10 5 15 0
vishay siliconix SIA921EDj document number: 64734 s12-2731-rev. c, 12-nov-12 www.vishay.com 5 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 0.1 t a = 25 c single p u lse 100 s limited b yr ds(on) * b v dss limited 1ms 10 ms 100 ms 1s,10s dc v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified - drain c u rrent (a) i d current derating* 0 2 4 6 8 10 12 0 255075100125150 package limited t c - case temperat u re (c) i d - drain c u rrent (a) power derating 0 2 4 6 8 25 50 75 100 125 150 t c - case temperat u re (c) po w er dissipation ( w )
www.vishay.com 6 document number: 64734 s12-2731-rev. c, 12-nov-12 vishay siliconix SIA921EDj this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact:: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64734 . normalized thermal transient im pedance, junction-to-ambient 1 0.1 0.01 normalized ef fective t ransient thermal impedance 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 square wave pulse duration (s) single pulse 0.02 0.05 0.1 0.2 duty cycle = 0.5 1. duty cycle, d = 2. per unit base = r th ja = 85 c/w 3. t jm - t a = p dm z th ja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm normalized thermal transient impedance, junction-to-case 10 -3 10 -2 10 -1 10 -4 1 0.01 square wave pulse duration (s) normalized ef fective t ransient thermal impedance duty cycle = 0.5 0.2 0.1 single pulse 0.02 0.05
vishay siliconix package information document number: 73001 06-aug-07 www.vishay.com 1 powerpak ? sc70-6l dim single pad dual pad millimeters inches millimeters inches min nom max min nom max min nom max min nom max a 0.675 0.75 0.80 0.027 0.030 0.032 0.675 0.75 0.80 0.027 0.030 0.032 a1 0 - 0.05 0 - 0.002 0 - 0.05 0 - 0.002 b 0.23 0.30 0.38 0.009 0.012 0.015 0.23 0.30 0.38 0.009 0.012 0.015 c 0.15 0.20 0.25 0.006 0.008 0.010 0.15 0.20 0.25 0.006 0.008 0.010 d 1.98 2.05 2.15 0.078 0.081 0.085 1.98 2.05 2.15 0.078 0.081 0.085 d1 0.85 0.95 1.05 0.033 0.037 0.041 0.513 0.613 0.713 0.020 0.024 0.028 d2 0.135 0.235 0.335 0.005 0.009 0.013 e 1.98 2.05 2.15 0.078 0.081 0.085 1.98 2.05 2.15 0.078 0.081 0.085 e1 1.40 1.50 1.60 0.055 0.059 0.063 0.85 0.95 1.05 0.033 0.037 0.041 e2 0.345 0.395 0.445 0.014 0.016 0.018 e3 0.425 0.475 0.525 0.017 0.019 0.021 e 0.65 bsc 0.026 bsc 0.65 bsc 0.026 bsc k 0.275 typ 0.011 typ 0.275 typ 0.011 typ k1 0.400 typ 0.016 typ 0.320 typ 0.013 typ k2 0.240 typ 0.009 typ 0.252 typ 0.010 typ k3 0.225 typ 0.009 typ k4 0.355 typ 0.014 typ l 0.175 0.275 0.375 0.007 0.011 0.015 0.175 0.275 0.375 0.007 0.011 0.015 t 0.05 0.10 0.15 0.002 0.004 0.006 ecn: c-07431 ? rev. c, 06-aug-07 dwg: 5934 e2 back s ide view of s ingle back s ide view of dual note s : 1. all dimen s ion s a re in millimeter s 2. p a ck a ge o u tline excl us ive of mold fl as h a nd met a l bu rr 3 . p a ck a ge o u tline incl us ive of pl a ting pin1 pin6 pin5 pin4 pin2 pin 3 a z detail z z d e k1 k2 c a1 k 3 k2 k2 e b b e pin6 pin5 pin4 pin1 pin 3 pin2 e1 e1 e1 l l k4 k k k d1 d2 d1 d1 k1 e 3
application note 826 vishay siliconix www.vishay.com document number: 70487 1 revision: 18-oct-13 application note recommended pad layout for powerpak ? sc70-6l dual 1 2.500 (0.09 8 ) 0.350 (0.014) 0.275 (0.011) 0.613 (0.024) 0.300 (0.012) 0.325 (0.013) 0.950 (0.037) 0.475 (0.019) 2.500 (0.09 8 ) 0.275 (0.011) 0.160 (0.006) 1.600 (0.063) dimensions in mm (inches) 0.650 (0.026) return to index
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